Electroless plating for depositing a metal on a base by decomposing a reductant in an aqueous solution of a metal salt and then reducing the metal salt without electrical energy is a technique that has been widely applied to functionalize the surfaces of insulating materials, for example, various plastics, glass, ceramic, or wood. For example, a component composed of an ABS resin, a polypropylene resin, or the like is subjected to electroless plating to produce a grille, a mark, or the like used for an automobile or a knob or the like used for a household electrical appliance. Such electroless plating is referred to as “decorative plating”. Furthermore, a through hole in a printed circuit board is subjected to electroless plating. Such electroless plating is referred to as “functional plating”.
However, an electroless-plating film often has low adhesion to the surface of each of the various materials. In particular, when electroless plating is applied to the production of the printed circuit board, an electroless plating film disadvantageously has low adhesion to an insulating material. In particular, when a method for forming a film by electroless plating is employed as a method for forming a metal layer directly on the surface of an insulating material, it is remarkably difficult to strongly bond the electroless plating film to the smooth surface of an insulating material having small surface roughness.
As a reason for this, in electroless plating, it is assumed that the film is deposited via a catalyst mainly composed of palladium or the like.
On the other hand, for example, in producing a printed circuit board having lines on a surface thereof, when an electroless plating film is provided on an insulating material, it is highly desirable that the electroless plating film be strongly bonded to a surface with a maximum degree of smoothness. The reasons are described as follows.
In printed circuit boards widely used for mounting electronic components and semiconductor devices, trends toward miniaturization and greater functionality of electronic devices nowadays strongly require higher density of wiring and a reduction in thickness. In particular, establishment of a method for forming a fine-pitch circuit having a line and space resolution of 25 μm/25 μm or less is an important challenge in the field of the printed circuit board. An example of an insulating layer used for the printed circuit board is an insulating sheet on which lines can be formed.
To form such a fine-pitch circuit, such an insulating sheet is required to have high adhesion to the fine-pitch circuit and adequately small surface roughness so as not to adversely affect the formation of the fine-pitch circuit. In other words, when the fine-pitch circuit is formed, a line shape, a line width, a line thickness, or the like cannot be satisfactorily achieved according to the design unless the irregularities of the surface of the insulating sheet are controlled as small as possible. Accordingly, it is highly desirable that the electroless plating film be strongly bonded to a surface with a maximum degree of smoothness.
In recent years, to improve information-processing abilities in electronic devices, there have been advances in increases in speed and frequency of electrical signals transmitting through circuits on printed circuit boards used in the electronic devices. Thus, even when the electrical signals have higher frequencies, the printed circuit boards are required to maintain electrical reliability and to suppress a reduction in the transmission rate of the electrical signals through the circuit and the loss of the electrical signals through the circuit. In particular, in printed circuit boards, such as multilayer flexible printed circuit boards and build-up printed circuit boards mounting semiconductor chips by flip-chip, the increases in speed and frequency of the electrical signals is significant. When electrical signals have higher speeds and higher frequencies, the surface roughness of the surface of a conducting circuit is desirably minimized for reducing the transmission loss of the signals. Accordingly, also from the standpoint of a material that permits increases in speed and frequency of electrical signals, it is necessary that the electroless plating film be strongly bonded to the surface of an insulating sheet with low surface roughness.
The most preferred insulating sheet for forming fine lines is an insulating sheet functioning as an insulating layer having a surface with very slight irregularities and sufficiently high adhesion to fine lines.
Known insulating sheets used for printed circuit boards have adhesion to electroless-plating films by anchoring effects of roughened surfaces obtained by various processes (for example, see Patent Document 1). However, small surface roughness results in low adhesion between an electroless-plating film and a resin component, thereby limiting the formation of fine lines.
For example, to improve adhesion to circuit wiring provided on the surface of a resin component having small surface roughness, a process of forming a primary metal layer on a surface of a polyimide film by a physical method, such as evaporation or sputtering, and forming a copper layer, which is a good conductor, is disclosed (see Patent Document 2). In this case, the adhesion strength between the primary metal layer and the polyimide film is high. However, this adhesion is not induced by the chemical binding force between the polyimide film and the metal. The adhesion is caused by providing the primary layer, in other words, the adhesion results from the fact that the primary layer microscopically anchors to the surface of the base and is linked to the copper layer by a metal-to-metal bond. However, in this process, the primary layer is composed of a metal other than copper. Thus, the primary layer is not completely removed using an etching solution for copper, in some cases. As a result, migration resistance between lines may be impaired. Furthermore, the process has disadvantages of high cost and low productivity due to use of a vacuum process.
A technique of bonding layers with an interlayer insulating adhesive containing a polyimidesiloxane is disclosed (for example, see Patent Document 3). However, in the technique described in Patent Document 3, a polyimide having a siloxane structure is used as an interlayer adhesive and is used for bonding a circuit substrate. Use as a layer for providing an electroless-plating film thereon is not disclosed.
A resin-containing metal foil produced by applying a polyimide precursor having a siloxane structure onto the metal foil and laminating a plating metal layer is disclosed (Patent Document 4). However, with respect to a production process of the metal layer, electroless plating is described in parallel with chromium sputtering or the like. The relationship between the adhesion strength of an electroless plating film, which is believed to have low adhesion to an insulating material, and surface roughness of a surface intended to be provided with an electroless-plating film is not confirmed in Patent Document 4.
Accordingly, the adhesion of an electroless-plating film to a smooth surface is not described in any document. In the present circumstances, no material capable of strongly bonding an electroless-plating film to a smooth surface thereof is found so far.
Furthermore, an insulating resin material used for a printed circuit board is required to have not only adhesion between an electroless-plating film and the resin material but also lower linear expansivity, in some cases.
In producing a multilayer flexible printed circuit board or a build-up circuit board, an insulating sheet is laminated to a conducting circuit provided on a substrate. The insulating sheet is required to have the ability to flow and fill in gaps between lines in the circuit in lamination; and to strongly adhere to the conducting circuit and to an insulating film having the circuit. That is, the insulating sheet is required to have satisfactory adhesion to an inner circuit, a substrate, and the like and flowability to the extent that the insulating sheet can fill in the gaps between lines in the circuit.
Furthermore, in producing a printed circuit board, the formation of a via hole, which electrically connects both sides of the circuit board, is essentially required. Thus, in such a printed circuit board, in general, steps, such as a via hole-forming step by laser, a desmearing step, a catalyst-adding step, and an electroless-copper-plating step, are performed to form lines. Moreover, usually, a semi-additive process including a step of forming a resist film, a step of subjecting the exposed portion of an electroless-plating film to electrolytic copper plating, a step of removing the resist film, and a step of etching an excess of the electroless-plating film is often employed for forming fine lines. Accordingly, the adhesion between the fine lines and the insulating layer more preferably endures these processes.
By using insulating sheets that satisfy the above-described requirements, high-density printed circuit boards used for electronic devices that require high-speed and high-frequency electrical signals can be provided. Therefore, the realization of such insulating sheets has been strongly desired. However, any of Patent Documents 1 to 4 does not describe the fact that an electroless-plating film can be strongly bonded to a smooth surface. Furthermore, any of these documents does not describe about an application example to a build-up circuit board or the like and about durability to these processes. In addition, usage of an insulating sheet facing an inner circuit provided in advance and inner circuit-embedding properties are not considered.
Furthermore, in insulating materials for printed circuit boards used in electronic devices, from the standpoint of the maintenance of adhesion to components mounted and a conducting layer at high temperatures, as described above, trends toward lower linear expansivity of the insulating material have been demanded. In achieving higher performance and a speedup, the strength of semiconductor elements may decrease (become brittle). Furthermore, trends toward higher densities of printed circuit boards require mounting of components and substrates with higher accuracy, thereby reducing the allowable ranges of misalignments. When the linear expansion coefficient of the substrate is significantly different from that of the element, a change in the temperature of the substrate mounting the element results in differences in dimensions of the substrate and the element. As a result, stress occurs, causing the breakage of the connection between the substrate and the element and the breakage of the element. To avoid such problems, materials for printed circuit boards are required to have linear expansion coefficients close to those of semiconductor elements. In other words, materials for printed circuit boards are required to have lower linear expansion coefficients.
Any of Patent Documents 1 to 4 does not describe the fact that an electroless-plating film can be strongly bonded to a smooth surface. Furthermore, any of these documents does not describe about low linear expansivity. The point of a reduction in the linear expansion coefficient of the circuit board is not considered.
From the standpoint of decreasing linear expansion coefficient of a material, a technique for controlling a linear expansion coefficient and viscosity by incorporating a filler in a sealing resin for a semiconductor device is disclosed (see Patent Document 5). However, the technique does not relate to an interlayer insulating material for a printed circuit board and has not provided a material that has satisfactory heat resistance and processability and that is suitably used for a printed circuit board.
Attempts have been made to reduce linear expansion coefficients by incorporating inorganic fillers in epoxy adhesive materials, which are often used for circuit boards (Patent Documents 6 to 8). In insulating resin compositions described in Patent Documents 6 to 8, the incorporation of the inorganic fillers achieves reductions in linear expansion coefficients. However, the incorporation of the inorganic fillers increases the surface roughness of the adhesive material. As a result, a surface having low surface roughness required for the formation of fine circuits cannot be obtained. Thus, fine lines cannot be formed. Furthermore, the surface roughness of a conducting circuit provided on the insulating material also increases inevitably. The realization of high-speed and high-frequency electrical signals increases the transmission loss of signals. As a result, the insulating resin compositions cannot correspond to the high-speed and high-frequency electrical signals. Furthermore, as a result of studies by the inventors, the inventors found that the incorporation of the inorganic filler disadvantageously reduces insulation between lines in the circuit. Specifically, the present inventors found the following: Electroless plating copper is deposited in a minute gap between the insulating resin and the bottom of the filler exposed in the surface. When an attempt is made to remove the electroless plating copper layer in a subsequent etching step, the etchant does not sufficiently reach the gap. As a result, the electroless plating copper remains in the gap to degrade the insulation.
Therefore, in a known insulating material containing an inorganic filler, the incorporation of the inorganic filler reduces the linear expansion coefficient but increases the surface roughness. That is, the incorporation of the inorganic filler can reduce the linear expansion coefficient but cannot achieve the surface roughness on which fine lines can be formed or capable of corresponding to the high-speed and high-frequency electrical signals.    [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2000-198907    [Patent Document 2] Japanese Unexamined Patent Application Publication No. 08-330728    [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2000-290606    [Patent Document 4] Japanese Unexamined Patent Application Publication No. 2002-264255    [Patent Document 5] Japanese Unexamined Patent Application Publication No. 07-66329    [Patent Document 6] Japanese Unexamined Patent Application Publication No. 2004-14611 (Publication Date: Jan. 15, 2004)    [Patent Document 7] Japanese Unexamined Patent Application Publication No. 2004-10660 (Publication Date: Jan. 15, 2004)    [Patent Document 8] Japanese Unexamined Patent Application Publication No. 2003-7138 (Publication Date: Jan. 10, 2003)